Threats of Soft Errors
Increasing exponentially with technology scaling, the soft error rate in even earth-bound embedded systems manufactured in deep sub-nanometer technology is projected become a serious design consideration. ITRS and many researchers expect soft error rate to increase exponentially at every technology. A high energy radiation particle, e.g., an alpha particle, a neutron, or a free proton, may strike the diffusion region of a CMOS transistor and produce charge which can result in toggling the logic value of the gates or flip-flops. This phenomenon of change in the logic state of a transistor is called a soft error or transient fault.
Challenges for Dependable Embedded Systems
In order to protect embedded systems from soft errors, conventional redundancy techniques such as TMR (Triple Modular Redundancy) and ECC (Error Correction Codes) incur high overheads in terms of area, power, and performance. For instance, the overheads of hardware and power for conventional TMR, which typically uses three functionally equivalent replicas of a logic circuit and a majority voter, exceed 200%. Since embedded systems are constrained with limited resources such as area, power and performance, there need several emerging challenges that embedded system designers are facing at microarchitectural level, at compilation, and at system level. For dependable embedded systems against soft error threats, solutions should accomplish high reliability with least overheads of power, performance, and area cost.
Relevant Publications
- Hwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee, “EXPERT: Effective and Flexible Error Protection by Redundant Multithreading”, DATE, Mar,2018
- Yohan Ko, “Comprehensive reliability evaluation for dependable embedded systems”, SIGDA PhD Forum at DAC (DAC) (Accepted)
- Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian, “Partitioning techniques for partially protected caches for resource-constrained embedded systems”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Sep, 2010.
- Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian, “Partially protected caches to reduce failures due to soft errors in multimedia applications”, IEEE Transactions on Very Large Scale Integration (VLSI) System (VLSI), Oct, 2009.
- Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian, “Mitigating the impact of hardware defects on multimedia applications: A cross-layer approach”, ACM International Conference on Multimedia (MM), Sep, 2008.
- Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian, “Data partioning techniques for partially protected caches to reduce soft error induced failures”, IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES), Aug, 2008.
- Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian, “Mitigating soft error failures for multimedia applications by selective data protection”, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Oct, 2006.
Research funding
- 정부부처: Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea government(MSIT)
- 과제번호: No. B0101-16-0644
- 과제명: Research Project on High Performance and Scalable Manycore Operating System
- 과제기간: 2014~2021년
- 총 액수: 약 3억